Analog Layout Staff Engineer
Marvell Technology(6 days ago)
About this role
This role involves developing next-generation high-speed SerDes IPs within Marvell’s Central Engineering Foundational IP team, focusing on advanced semiconductor technology processes and circuit layout. The position contributes to the creation of cutting-edge analog IPs that enable fast, reliable data handling.
Required Skills
- SerDes
- Cadence Virtuoso
- Mixed Signal
- Analog Design
- High Speed Layout
- Device Physics
- RC Extraction
- Physical Verification
- FinFET
- Circuit Layout
Qualifications
- Bachelor's or Master's Degree in Electrical/Electronics Engineering, Microelectronics or related fields
- 4 to 8 years of professional experience
About Marvell Technology
marvell.comDesigned for your current needs and future ambitions, Marvell delivers the data infrastructure technology transforming tomorrow’s enterprise, cloud, automotive, and carrier architectures for the better.
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