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Analog / Mixed-Signal Layout Engineer at Astera Labs - ApplyBlast

Analog / Mixed-Signal Layout Engineer

Astera Labs

11 days ago

4.3 on Glassdoor

Singapore, Singapore, Singapore

Onsite

Internship

Intern

0 applicants

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About this role

Astera Labs is seeking an Analog / Mixed-Signal Layout Engineer to join its ASIC team, focusing on high-performance compute and networking standards in advanced CMOS process nodes. The role requires a strong hardware engineering background with expertise in VLSI and computer architecture, alongside experience in design, verification, and validation of real-world systems. Candidates should possess hands-on knowledge of RTL design languages, verification methodologies, and scripting tools to support leading-edge design and verification tasks.

Responsibilities

Design and verify blocks using leading edge methodology and tools
Work on high-performance compute and networking standards in advanced CMOS process nodes
Collaborate with hyperscalers and ecosystem partners to unlock AI potential

Skills

Qualifications

BS in EE/CSMS in EE/CS

About Astera Labs

asteralabs.com

Headquarters

Santa Clara, California, United States

Company Size

201-500 employees

Founded

2017

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Astera Labs is a semiconductor company that builds purpose‑built connectivity silicon and system solutions for rack‑scale AI and modern data centers. They design high‑speed retimers, PHY/connectivity devices, interposers and companion firmware/software that extend signal reach, improve link reliability, and enable PCIe/CXL and other accelerator interconnects across cables and backplanes. Astera’s products add telemetry, error monitoring and management features to simplify integration for OEMs, cloud providers and hyperscalers. The company focuses on enabling scalable, low‑latency multi‑node AI training and inference systems.