ASIC Design Engineer Intern
Ambarella(2 months ago)
About this role
An RTL design engineer role focused on AI vision processors for edge camera applications. The position supports development of processor cores and accelerators that extract actionable data from high-resolution video streams. Work contributes to silicon and toolflow development for embedded vision products.
Required Skills
- Verilog
- System Verilog
- RTL Design
- VLSI Design
- Logic Design
- Synthesis
- Timing Closure
- Verification
- UVM
- C++
+7 more
Qualifications
- Master's Degree in Electrical/Electronics/Computer Engineering
About Ambarella
ambarella.comAmbarella's advanced imaging solutions make cameras smarter by extracting valuable data from high-resolution video streams.
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