ASIC Design Engineer

This role involves defining and documenting micro-architecture for next-generation ASIC designs while responsible for logic design and RTL entry to meet power, performance, and area targets. The position requires close collaboration with verification, emulation, physical design, and DFT teams to ensure design intent, timing closure, and coverage. The ideal candidate will work independently in a fast-paced startup environment to deliver high-performance infrastructure for AI workloads.