ASIC Design Engineering Intern - 2026
NVIDIA(1 month ago)
About this role
NVIDIA's PMU team develops a Power Management Unit IP used across datacenter, automotive, PC, and robotics chips. The PMU IP combines a RISC-V core with custom control logic to optimize chip power efficiency across idle and active scenarios. This internship supports evolution of the PMU micro-architecture to increase flexibility and scalability for future chips.
Required Skills
- Verilog
- Perl
- Python
- C++
- RISC-V
- Micro-Architecture
- IP Design
- ASIC Design
- Problem Solving
Qualifications
- Master Degree (Pursuing)
- Major in Electronic Science & Technology
About NVIDIA
nvidia.comNVIDIA invents the GPU and drives advances in AI, HPC, gaming, creative design, autonomous vehicles, and robotics.
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