ASIC Emulation and Verification Engineer

The ASIC Emulation and Verification Engineer bridges the gap between simulation and hardware acceleration by bringing up complex ASIC IP and SoC designs on Cadence Palladium emulation platforms. The role involves converting RTL databases into emulation-ready models, executing high-speed hardware acceleration, and supporting pre-silicon verification tasks. This position requires collaboration with firmware teams for early bring-up and debugging across both simulation and emulation environments.