ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |8-12 years| Pune)

The ASIC Engineering Design Verification Leader role involves creating verification documentation, developing testbench components, and running verification at block and chip levels for high-speed optical transceivers and silicon photonic platforms. The position requires expertise in SystemVerilog, Python, C, and UVM methodology to debug complex verification issues and ensure functional coverage. This role also includes post-silicon activities such as ATE test plan generation and release to production.