ASIC Physical Design Engineer

This role focuses on physical design from RTL to GSDII within the ASIC-PD team, covering tasks such as synthesis, formal check, partitioning, constraint management, and timing analysis. Candidates will collaborate across ASIC, P&R, DFT, SI, and ARCH teams to drive physical-friendly designs for the company's largest chip using advanced processes. The position requires developing and enhancing timing closure flows, managing floorplanning, and creating methodologies for both pre-layout and post-layout stages.