ASIC Physical Design Technical Lead

The ASIC Physical Design Technical Lead drives full-chip floorplanning and RTL-to-GDSII implementation for advanced process technologies, optimizing performance, power, and die size. This role involves collaborating with system, package, and IP teams to define signoff methodologies and enhance design flows using AI tools and low-power design practices. The position requires expertise in hierarchical implementation, timing closure, and physical design convergence to support Cisco's core hardware platforms.