Teradyne
The ASIC/FPGA Methodology Engineer will define, develop, and maintain methodologies and workflows for FPGA and ASIC design and verification. The role involves collaborating with design and verification teams, supporting RTL development, optimizing design flows, and implementing CI/CD pipelines in a Linux-based environment.
Headquarters
North Reading, Massachusetts, United States
Company Size
5001-10000 employees
Founded
1960
Teradyne offers cutting-edge technological solutions for modern problems through innovation expertise. Stay connected with Teradyne’s offerings. Learn more.
Headquarters
San Francisco, CA
Company Size
201-500 employees
Founded
2018
Industry
Technology
Glassdoor Rating
4.2 / 5
Sarah Johnson
Chief Executive Officer
Michael Chen
Chief Technology Officer
Emily Williams
VP of Engineering
David Rodriguez
VP of Product
Jessica Thompson
Chief Financial Officer
Andrew Park
VP of Sales
View leadership team, funding history,
and employee contacts for Teradyne.
129% above the average for this role
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