SiFive
A Power-Management/Reset/Clock Micro-Architect and RTL Design Engineer at SiFive designs power management, reset, and clocking solutions for RISC-V CPU and SoC IP designs. The role involves creating highly-configurable hardware solutions with the agility of software development.
Headquarters
Santa Clara, California, United States
Company Size
501-1000 employees
Founded
2015
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world.
Headquarters
San Francisco, CA
Company Size
201-500 employees
Founded
2018
Industry
Technology
Glassdoor Rating
4.2 / 5
Sarah Johnson
Chief Executive Officer
Michael Chen
Chief Technology Officer
Emily Williams
VP of Engineering
David Rodriguez
VP of Product
Jessica Thompson
Chief Financial Officer
Andrew Park
VP of Sales
View leadership team, funding history,
and employee contacts for SiFive.
SiFive to Power Next-Gen RISC-V AI Data Centers with NVIDIA NVLink Fusion
Jan 15, 2026
IP Logic Design Engineer
Intel
Rtl Design Principal Engineer Chennai Tamil Nadu India
Qualcomm Incorporated
SoC Power Architecture Engineer
Samsung US
Rtl Design Soc Sr Engineer Bangalore Karnataka India
Qualcomm Incorporated
Asic Design Engineer Low Power Ai Subsystems Markham Ontario Canada
Qualcomm Incorporated
IP Logic Design Engineer
Intel