Design Engineer
Astera Labs(1 month ago)
About this role
Astera Labs is establishing a new R&D center in Israel, focused on developing complex semiconductor chips to support AI infrastructure. They are seeking a Senior VLSI Design Engineer to design digital blocks for high-performance connectivity projects that power large AI clusters. The role involves building innovative hardware and contributing to the company's next-generation AI solutions.
Required Skills
- Verilog
- SystemVerilog
- RTL Design
- Scripting
- Synthesis
- Timing Analysis
- Power Management
- Debugging
- Connectivity Protocols
- High-Speed Serial
Qualifications
- BSc in Electrical Engineering or related
- 3+ years in logic design
About Astera Labs
asteralabs.comAstera Labs is a semiconductor company that builds purpose‑built connectivity silicon and system solutions for rack‑scale AI and modern data centers. They design high‑speed retimers, PHY/connectivity devices, interposers and companion firmware/software that extend signal reach, improve link reliability, and enable PCIe/CXL and other accelerator interconnects across cables and backplanes. Astera’s products add telemetry, error monitoring and management features to simplify integration for OEMs, cloud providers and hyperscalers. The company focuses on enabling scalable, low‑latency multi‑node AI training and inference systems.
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