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Design Engineering Architect at Cadence - ApplyBlast

Design Engineering Architect

Cadence

1 month ago

4.0 on Glassdoor

Shanghai, Shanghai, China

Onsite

Full Time

Senior

0 applicants

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About this role

This role serves as the primary Korea-based expert for the UFS/Unipro/MPHY/RMMI protocol stack, working directly with customers to debug, integrate, and deploy complex memory protocol IP on hardware emulation platforms. The position involves collaborating with the global Memory Model Portfolio R&D team to solve technical challenges, mentor engineers, and ensure successful product deployments across various industries. It requires deep protocol expertise, strong debugging skills, and the ability to translate customer needs into actionable solutions for the development team.

Responsibilities

Serve as primary customer interface for protocol integration and system-level debugging
Triage and analyze field issues to scope and schedule repair of model defects
Mentor design engineers in protocol understanding, RTL code, and verification methodology

Skills

Qualifications

Master's degree in Electrical EngineeringPhD

About Cadence

cadence.com

Headquarters

San Jose, California, United States

Company Size

10001+ employees

Founded

1988

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Cadence is a company specializing in electronic design automation (EDA) software and engineering services for the semiconductor and electronics industries. Their tools enable design and verification of integrated circuits, systems on chips, and electronics systems, streamlining the development process for engineers and designers. With a commitment to innovation and excellence, Cadence empowers companies to enhance product performance and reduce time to market through advanced simulation, verification, and design tools.