Design for Test Engineering Intern

A Design For Test (DFT) Engineer Intern at Marvell's Bucharest Design Center will learn system-on-chip implementation and chip-level DFT methodologies for complex custom ASIC designs. The role provides exposure to DFT insertion and verification flows, automated test pattern generation (ATPG), and Memory Built-In Self-Test (MBIST) while working with Marvell’s DFT team and industry-standard tools.