Design for Test Engineering Intern
Marvell Technology
About this role
A Design For Test (DFT) Engineer Intern at Marvell's Bucharest Design Center will learn system-on-chip implementation and chip-level DFT methodologies for complex custom ASIC designs. The role provides exposure to DFT insertion and verification flows, automated test pattern generation (ATPG), and Memory Built-In Self-Test (MBIST) while working with Marvell’s DFT team and industry-standard tools.
Skills
Qualifications
About Marvell Technology
marvell.comDesigned for your current needs and future ambitions, Marvell delivers the data infrastructure technology transforming tomorrow’s enterprise, cloud, automotive, and carrier architectures for the better.
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About Marvell Technology
Headquarters
San Francisco, CA
Company Size
201-500 employees
Founded
2018
Industry
Technology
Glassdoor Rating
4.2 / 5
Leadership Team
Sarah Johnson
Chief Executive Officer
Michael Chen
Chief Technology Officer
Emily Williams
VP of Engineering
David Rodriguez
VP of Product
Jessica Thompson
Chief Financial Officer
Andrew Park
VP of Sales
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and employee contacts for Marvell Technology.
Salary
$40k – $59k
per year