Design for Test Engineering Intern
Marvell Technology(26 days ago)
About this role
A Design For Test (DFT) Engineer Intern at Marvell's Bucharest Design Center will learn system-on-chip implementation and chip-level DFT methodologies for complex custom ASIC designs. The role provides exposure to DFT insertion and verification flows, automated test pattern generation (ATPG), and Memory Built-In Self-Test (MBIST) while working with Marvell’s DFT team and industry-standard tools.
Required Skills
- Design For Test
- ASIC Design
- SoC
- ATPG
- MBIST
- Verilog
- VHDL
- Scripting
- Linux
- Circuit Simulation
Qualifications
- Pursuing BS Degree in Electronics or Computer Science
About Marvell Technology
marvell.comDesigned for your current needs and future ambitions, Marvell delivers the data infrastructure technology transforming tomorrow’s enterprise, cloud, automotive, and carrier architectures for the better.
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