Design Verification Engineer | FPGA

The Design Verification Engineer at Boeing in El Segundo, CA, is responsible for developing and maintaining FPGA verification environments, including SystemVerilog/UVM testbenches and reusable components. The role involves creating verification plans, integrating C-based tests, and driving coverage closure to ensure hardware/software functionality. This position requires collaboration with cross-functional teams to define verification scope, debug issues, and mentor junior engineers.