SiFive

Design Verification Engineer to Staff Engineer (Unit Level Test)

SiFive(2 months ago)

HybridFull TimeMedior$128,412 - $170,292 (estimated)Engineering
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About this role

A Design Verification Engineer at SiFive works within the engineering organization to support verification of RISC-V processor and SoC designs. The role collaborates with cross-functional teams to ensure high-quality, high-performance compute platforms through scalable verification approaches. The position is based in Taiwan and contributes to SiFive’s mission of advancing RISC-V technology.

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Required Skills

  • SystemVerilog
  • UVM
  • Verilog
  • C++
  • Makefiles
  • Scripting
  • Assertions
  • Checkers
  • Testbenches
  • VerificationIP

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SiFive

About SiFive

sifive.com

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world.

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