Design Verification Engineer to Staff Engineer (Unit Level Test)
SiFive(2 months ago)
About this role
A Design Verification Engineer at SiFive works within the engineering organization to support verification of RISC-V processor and SoC designs. The role collaborates with cross-functional teams to ensure high-quality, high-performance compute platforms through scalable verification approaches. The position is based in Taiwan and contributes to SiFive’s mission of advancing RISC-V technology.
Required Skills
- SystemVerilog
- UVM
- Verilog
- C++
- Makefiles
- Scripting
- Assertions
- Checkers
- Testbenches
- VerificationIP
+6 more
About SiFive
sifive.comAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world.
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