Design Verification Engineer

OpenAI(3 months ago)

San Francisco, CAOnsiteFull TimeSenior$310,000 - $380,000Scaling

About this role

A Design Verification Engineer at OpenAI is responsible for ensuring the functional correctness and reliability of cutting-edge machine learning accelerators and custom silicon. The role involves defining and executing verification plans, developing testbenches in SystemVerilog/UVM, and collaborating with architecture, RTL, software, and systems teams to verify custom IP blocks and full SoCs. The engineer will also address bugs and contribute to regression and coverage analysis efforts to ensure the delivery of production-grade silicon for AI workloads.

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Required Skills

Design Verification
Functional Correctness
Custom IP Blocks
Verification Plans
Testbenches Development
SystemVerilog
UVM
Stimulus Generators
Bug Triage
Root Cause Analysis

+7 more

Qualifications

BS/MS in EE/CE/CS or equivalent
3+ years of experience in hardware verification
Proficient in SystemVerilog
Proficient in UVM
Familiarity with VCS, Questa, Verdi

About OpenAI

openai.com

The company specializes in providing innovative solutions to enhance online experiences for businesses and consumers. It offers a range of products and services designed to streamline operations, improve customer engagement, and drive growth in the digital landscape. With a focus on user experience and cutting-edge technology, the company aims to empower businesses to thrive in a rapidly evolving market.