DFT Architect

The DFT Architect will own the design-for-test strategy for the company's electronic IC, setting coverage assessment and signoff standards while collaborating with RTL and physical design teams to integrate testability from the beginning. This role involves defining the DFT architecture for multiple ASIC devices, including scan, ATPG, and MBIST, and establishing the team's execution processes. The position requires leading the handoff to post-silicon test programs and ensuring comprehensive test coverage across all product development phases.