DFT Architect/Manager/Sr. Manager

The DFT Architect/Manager/Sr. Manager at Velaura AI leads the definition, implementation, and execution of Design-for-Test strategies for next-generation AI and high-performance computing silicon. This role drives test architecture, methodology, and implementation across complex ASIC/SoC designs to ensure high test quality, manufacturability, and production readiness. The position involves close collaboration with architecture, verification, physical design, and manufacturing teams to integrate robust DFT features and support successful silicon bring-up and yield ramp.