Digital System Verification Engineer
Eightfold(6 days ago)
About this role
This role involves performing design verification using UVM for complex module and system designs in Verilog. The engineer collaborates with architects and developers to ensure system requirements are met and designs verification strategies to verify the customer experience. It also includes defining system specifications, coordinating subsystem designs, and mentoring interns and new hires.
Required Skills
- Verilog
- SystemVerilog
- UVM
- Linux
- C++
- Shell Scripting
- Python
- Computer Architecture
- AXI
- CPI
About Eightfold
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