Distinguished Formal Verification
Astera Labs(6 hours ago)
About this role
Astera Labs is seeking a highly experienced formal verification engineer to lead and develop verification strategies for its advanced connectivity products in the AI infrastructure space. The role involves defining methodologies, mentoring teams, and representing the company in industry forums.
Required Skills
- SystemVerilog
- Verilog
- Python
- Perl
- Formal Verification
- Assertions
- Model Checking
- CXL
- PCIe
- Ethernet
Qualifications
- BS in Electrical Engineering, Computer Engineering, or Computer Science
About Astera Labs
asteralabs.comAstera Labs is a semiconductor company that builds purpose‑built connectivity silicon and system solutions for rack‑scale AI and modern data centers. They design high‑speed retimers, PHY/connectivity devices, interposers and companion firmware/software that extend signal reach, improve link reliability, and enable PCIe/CXL and other accelerator interconnects across cables and backplanes. Astera’s products add telemetry, error monitoring and management features to simplify integration for OEMs, cloud providers and hyperscalers. The company focuses on enabling scalable, low‑latency multi‑node AI training and inference systems.
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