Engineer 3, Integrated Circuit Package Design

Engineering Intern - University (25 days ago)

Tempe, AZOnsiteFull TimeMedior$0 - $120,000Engineering

About this role

Engineer 3 (Integrated Circuit Package Design Engineer) at Arizona State University’s SWAP Hub within the DoD Microelectronics Commons, focused on advancing microelectronics packaging to support national defense and commercial applications. This grant-funded role is based on ASU’s Tempe campus and requires U.S. person eligibility.

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Required Skills

Cadence Allegro
Package Design
PCB Design
Signal Integrity
HFSS
EDA Tools
Linux Unix
Scripting
Layout
DRC

+1 more

Qualifications

Bachelor's Degree in Engineering
Master's Degree in Engineering
US Person

About Engineering Intern - University

asu.edu

Arizona State University (ASU) is a large public research university headquartered in Tempe, Arizona, with multiple campuses and a comprehensive online education arm. The institution emphasizes interdisciplinary research and innovation—ranking No. 9 in the U.S. and No. 14 globally for interdisciplinary science—and focuses on preparing students for future careers. ASU offers a broad array of undergraduate, graduate, and professional programs across science, technology, humanities, and public service, with extensive industry partnerships and research centers. The university prioritizes access, entrepreneurship, sustainability, and community engagement to translate research into real-world impact.

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