Formal Verification Manager

Astera Labs(30 days ago)

IsraelOnsiteFull TimeSenior$130,000 - $160,000Research & Development

About this role

Astera Labs is establishing a new R&D center in Israel focused on developing complex semiconductor chips for AI applications. The company is seeking a Formal Verification Manager to lead verification activities, build and mentor a team, and establish verification methodologies to ensure the correctness of their designs before production.

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Required Skills

Formal Verification
RTL Design
Verification Methodologies
UVM
SystemVerilog
Jasper
VC Formal
Networking Standards
High-Speed Serial Interface
Chip Design

About Astera Labs

asteralabs.com

Astera Labs is a semiconductor company that builds purpose‑built connectivity silicon and system solutions for rack‑scale AI and modern data centers. They design high‑speed retimers, PHY/connectivity devices, interposers and companion firmware/software that extend signal reach, improve link reliability, and enable PCIe/CXL and other accelerator interconnects across cables and backplanes. Astera’s products add telemetry, error monitoring and management features to simplify integration for OEMs, cloud providers and hyperscalers. The company focuses on enabling scalable, low‑latency multi‑node AI training and inference systems.

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