Full Chip Timing Modeling and Integration Engineer
France Cars SAS AAA(18 days ago)
About this role
Altera is looking for a Full Chip Engineer to develop and execute full-chip timing methodologies for next-generation FPGA products in a fast-paced, high-performance environment. The role involves cross-functional collaboration, troubleshooting, and ensuring timing analysis quality for advanced process technologies.
Required Skills
- Verilog
- Python
- Tcl
- Static Timing Analysis
- Design Constraints
- Library QA
- Timing Modeling
- Integration
- Debugging
- SPICE
About France Cars SAS AAA
bloomberg.comBloomberg is a global leader in financial information and technology, providing data, news, and analytics to financial professionals around the world. The company offers an array of products and services, including the Bloomberg Terminal, which delivers real-time data and insights for trading, investment, and risk management. With a commitment to innovation, Bloomberg combines cutting-edge technology with extensive market expertise to empower financial professionals in making informed decisions.
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