Interconnect Design Engineer

SiFive seeks a Staff Level Hardware Engineer to design industry-leading CPU and interconnect IP, specifically optimizing the TileLink interconnect and cache controllers using the Chisel framework. This role involves architecting highly configurable RTL generators in Scala and contributing to SiFive's integrated Chisel/FIRRTL design and verification ecosystem. The successful candidate will drive the adoption of RISC-V architecture across various SOC designs while collaborating on high-performance verification and documentation.