Interconnect Design Engineer

SiFive is seeking a Staff Level Hardware Engineer to design industry-leading CPU and interconnect IP, specifically focusing on RISC-V and TileLink architectures. The role involves architecting highly-configurable hardware generators using the Chisel library in Scala to enhance existing IP and develop new solutions for diverse vertical applications. This position requires deep expertise in RTL design, cache coherency, and software engineering principles to deliver high-performance infrastructure logic.