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Interconnect Design Engineer at SiFive - ApplyBlast

Interconnect Design Engineer

SiFive

3 months ago

3.9 on Glassdoor

Santa Clara, CA

Onsite

Full Time

Senior

0 applicants

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About this role

SiFive is seeking a senior staff hardware engineer to design industry-leading CPU and interconnect IP, specifically focusing on RISC-V and TileLink architectures. The role involves architecting highly-configurable hardware generators using the Chisel library in Scala to enhance time-to-market and performance. This position requires deep expertise in RTL design, cache coherency, and software engineering principles to build scalable infrastructure for diverse vertical applications.

Responsibilities

Architect and implement enhanced TileLink interconnects and cache controllers as RTL generators
Design extensive configurability in hardware to optimize multi-core and multi-system coherence
Integrate new design content into the Chisel/FIRRTL framework for automated verification
Perform initial sandbox verification and collaborate on thorough verification test plans
Maintain comprehensive documentation and foster a culture of collaborative design

Skills

Qualifications

BS in EE, CE, CS or related technical disciplineMS in EE, CE, CS or related technical discipline

About SiFive

sifive.com

Headquarters

Santa Clara, California, United States

Company Size

501-1000 employees

Founded

2015

View Profile

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world.