Intern, Architect - Link Architecture and Analysis

Ayar Labs is seeking a motivated graduate or Ph.D. intern to join the CTO architecture team, focusing on co-packaged optics (CPO) and optical I/O chiplets to revolutionize AI compute hardware scaling. The intern will collaborate with mixed-signal designers, photonics engineers, and system architects to evaluate packaging paradigms and model architecture performance. This role involves working on EIC/PIC co-optimization and analyzing electro-optical boundaries and signal integrity. The position is based on-site in San Jose, CA, from May to August 2027.