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© All Rights Reserved. ApplyBlast.com
Altera
The IP Design PEY Intern role at Altera involves developing and verifying cutting-edge FPGA RTL and IP cores for external memory and high-speed I/O interfaces. The position requires collaboration with cross-functional teams to ensure seamless integration and optimization of IP solutions for applications in data centers and machine learning. Candidates will engage in architecture design, verification, and technical documentation while supporting new product releases and customer needs.
Headquarters
San Jose, California, United States
Company Size
1001-5000 employees
Founded
1983
Altera empowers innovators with scalable FPGA and SoC solutions, spanning high-performance to power- and cost-optimized devices. These devices are designed for cloud, network, and edge applications, enabling flexible acceleration and deployment. The company positions itself as a catalyst for innovation, providing adaptable hardware platforms for diverse workloads. Altera’s mission is to accelerate innovators by delivering versatile programmable logic solutions.