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Junior Design Verification Engineer at Astera Labs - ApplyBlast

Junior Design Verification Engineer

Astera Labs

4 months ago

4.3 on Glassdoor

Tel Aviv-Yafo, Tel Aviv District, Israel

Onsite

Full Time

Junior

0 applicants

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About this role

Astera Labs is seeking a Junior Design Verification Engineer to join a new strategic R&D center in Israel focused on developing complex semiconductor chips for AI infrastructure. In this role, you will develop SystemVerilog-based verification environments and testbenches to validate high-performance digital blocks and ensure connectivity solutions meet rigorous demands. This position offers the opportunity to build verification methodologies from the ground up while collaborating with design engineers to resolve hardware bugs.

Responsibilities

Develop and maintain SystemVerilog/UVM-based verification components
Create traffic generators and monitors for robust digital testing
Implement functional coverage models to achieve verification closure
Collaborate with design engineers to root-cause hardware bugs

Skills

Qualifications

Bachelor's degree in Electrical or Computer EngineeringProficiency in C/C++ or PythonFamiliarity with Verilog or SystemVerilog

About Astera Labs

asteralabs.com

Headquarters

Santa Clara, California, United States

Company Size

201-500 employees

Founded

2017

View Profile

Astera Labs is a semiconductor company that builds purpose‑built connectivity silicon and system solutions for rack‑scale AI and modern data centers. They design high‑speed retimers, PHY/connectivity devices, interposers and companion firmware/software that extend signal reach, improve link reliability, and enable PCIe/CXL and other accelerator interconnects across cables and backplanes. Astera’s products add telemetry, error monitoring and management features to simplify integration for OEMs, cloud providers and hyperscalers. The company focuses on enabling scalable, low‑latency multi‑node AI training and inference systems.