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Layout Design Engineer II (SerDes) at Cadence - ApplyBlast

Layout Design Engineer II (SerDes)

Cadence

5 months ago

4.0 on Glassdoor

Onsite

Full Time

Executive

0 applicants

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About this role

This role involves performing custom transistor-level layout for high-speed SerDes blocks and analog front-ends for next-generation high-speed interface IP. The engineer will partner with circuit designers to optimize floorplanning, parasitic-sensitive routing, and signal integrity while supporting advanced physical design implementation activities. Collaboration with cross-functional teams is essential to deliver high-quality, manufacturable designs for various market applications.

Responsibilities

Perform custom transistor-level layout for high-speed SerDes blocks and analog front-ends
Optimize floorplanning, parasitic-sensitive routing, and signal integrity for manufacturing readiness
Support physical design implementation including device placement, routing, and shielding
Run and debug physical verification flows such as DRC, LVS, and ERC checks
Apply advanced layout techniques like common-centroid structures and dummy fill

Skills

Qualifications

BS in Electronic EngineeringBS in MicroelectronicsBS in Computer Engineering

About Cadence

cadence.com

Headquarters

San Jose, California, United States

Company Size

10001+ employees

Founded

1988

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Cadence is a company specializing in electronic design automation (EDA) software and engineering services for the semiconductor and electronics industries. Their tools enable design and verification of integrated circuits, systems on chips, and electronics systems, streamlining the development process for engineers and designers. With a commitment to innovation and excellence, Cadence empowers companies to enhance product performance and reduce time to market through advanced simulation, verification, and design tools.