Lead DFT Engineer (Edge Computing)

The Lead DFT Engineer will define and implement the end-to-end design‑for‑test architecture for complex edge‑focused SoCs, overseeing scan insertion, ATPG, and memory/logic BIST while ensuring manufacturability and reliability. The role also leads post‑silicon validation on automated test equipment, collaborating with design, physical design, and yield teams to optimize test coverage, area, power, and timing.