Lead DFT Engineer

A Digital Design Engineer at NXP focuses on scan insertion, ATPG, and GLS within DFT architectures to support implementation teams. The role requires proficiency in industry-standard tools like Mentor Tessent and Synopsys DFT Compiler, along with experience in fault modeling and coverage analysis. Candidates must be familiar with IEEE 1149.1 and IEEE 1687 standards while collaborating effectively across functions.