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Lead RTL Design Engineer - ( Mixed-Signal IPs) at Silicon Labs - ApplyBlast

Lead RTL Design Engineer - ( Mixed-Signal IPs)

Silicon Labs

7 months ago

4.2 on Glassdoor

Hyderabad

Onsite

Full Time

Senior

0 applicants

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About this role

An RTL Design Engineer for Mixed-Signal IPs at Silicon Labs develops and verifies digital RTL blocks within mixed-signal subsystems. The role involves collaboration with analog teams and SoC integration to ensure high-quality, low-power, and functionally robust IP delivery.

Skills

Qualifications

B.E./B.Tech or M.S./M.Tech in Electrical Engineering, Electronics, or Computer Engineering5–10 years of experience in digital RTL design with strong exposure to mixed-signal IP or subsystem developmentProficiency in Verilog/SystemVerilog and experience with synthesis and static verification flows (lint, CDC)Familiarity with analog/mixed-signal concepts such as signal sampling, clocking, calibration, and power managementHands-on experience with mixed-signal co-simulation tools (Cadence AMS Designer, Synopsys VCS AMS, etc.)