Lead RTL Design Engineer

About this role

Responsibilities

• Microarchitecture definition and RTL implementation across dataflow execution fabric, memory subsystem, on-chip interconnect/NoC, low-power logic, and standard peripheral IP
• On-chip interconnects and system integration, balancing performance, scalability, and implementation constraints
• Memory subsystem and system architecture, defining interface to memory subsystem and ensuring scalable model for software and future system expansion
• Reconfiguration and execution model, leading architecture of configuration, scheduling, and execution of workloads on the fabric, including multi-kernel support and interaction with host systems
• Power management and low-power design, driving power architecture across the design, including clocking, reset, power domains, and low-power strategies