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Home | Ultra-Low-Power Infrastructure for the AI Era
This role focuses on designing, implementing, and optimizing RTL for the memory subsystem of the Velaura SoC, including memory controllers and fabric interfaces. The engineer will own memory controller and PHY integration, drive high-speed low-power design, and collaborate with software teams to define hardware interfaces and performance-critical interactions. The position requires analyzing memory path bottlenecks and optimizing designs for performance, power, area, and reliability.
Delivering proven, breakthrough, ultra-low-power compute for cloud, edge, and physical AI applications.
Headquarters
San Francisco, CA
Company Size
201-500 employees
Founded
2018
Industry
Technology
Glassdoor Rating
4.2 / 5
Sarah Johnson
Chief Executive Officer
Michael Chen
Chief Technology Officer
Emily Williams
VP of Engineering
David Rodriguez
VP of Product
Jessica Thompson
Chief Financial Officer
Andrew Park
VP of Sales
View leadership team, funding history,
and employee contacts for Home | Ultra-Low-Power Infrastructure for the AI Era.
15% above the average for this role