ML Silicon Performance Lead

The ML Silicon Performance Lead drives hardware/software co-design for AI-native silicon architecture, connecting model and workload requirements with compute, memory, and specialized acceleration capabilities to maximize performance and efficiency. This role involves partnering with ML research, compiler, and silicon architecture teams to shape kernel implementations, optimize data movement, and validate architectural improvements through performance modeling and simulation. The position focuses on balancing model quality, numerical behavior, and implementation cost while guiding hardware design decisions for large-scale AI workloads.