Modelling Lead (SystemC / Virtual-Platform Architect)

This critical role involves building a SystemC/TLM-2.0 virtual platform and executable models for complex SoCs before silicon exists. The engineer will define architecture models for datapath latency, throughput, and buffer sizing to act as golden checkers for the verification team. Working closely with architecture and firmware teams, the role ensures model fidelity spans hardware micro-architecture and embedded software to unblock parallel development.