PCIe ASIC Design Engineer
Cornelis Networks
About this role
Cornelis Networks is seeking a Senior ASIC Design Engineer to lead PCIe controller integration into next-generation SoCs for high-performance computing and AI data centers. The role involves collaboration across multiple teams to develop and validate high-speed interconnects that drive innovation in demanding computational environments.
Skills
About Cornelis Networks
cornelis.comCornelis Networks builds the world's first lossless, zero-congestion network engineered for AI and high-performance computing (HPC). Their networking solution eliminates congestion to deliver higher throughput, lower latency, and predictable scaling for GPU/accelerator clusters running large-scale training and inference workloads. By addressing traffic patterns that break legacy fabrics, Cornelis unlocks better hardware utilization and performance for data centers and AI infrastructure operators.
About Cornelis Networks
Headquarters
San Francisco, CA
Company Size
201-500 employees
Founded
2018
Industry
Technology
Glassdoor Rating
4.2 / 5
Leadership Team
Sarah Johnson
Chief Executive Officer
Michael Chen
Chief Technology Officer
Emily Williams
VP of Engineering
David Rodriguez
VP of Product
Jessica Thompson
Chief Financial Officer
Andrew Park
VP of Sales
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Salary
$149k – $201k
per year