PCIe/CXL Subsystem Design Engineer

The role focuses on defining micro‑architecture, implementing RTL, and integrating PCIe/CXL subsystems for Marvell's custom chips used in hyperscale cloud, AI, and data‑center applications. The engineer will collaborate with architecture, verification, physical design, and firmware teams to ensure high‑performance, low‑latency designs and support silicon bring‑up and post‑silicon debugging.