PCIe/CXL Verification Engineer

The role focuses on end‑to‑end verification of PCIe Gen6/Gen7 and CXL 3.0/4.0 subsystems, including test planning, UVM/SystemVerilog environment development, and coverage closure. The engineer will collaborate with design, architecture, firmware, and validation teams to ensure protocol compliance, performance metrics, and robust silicon delivery for Marvell's data‑center and AI products.