Physical Design, Power Integrity, or Signoff

This role focuses on leading full-chip and subsystem-level power distribution network signoff for complex SoCs, ensuring power integrity closure across various operational modes. The position involves defining signoff criteria, driving package-aware analysis, and collaborating with cross-functional teams to optimize power grid architecture and thermal performance. It requires mentoring engineers, developing next-generation signoff methodologies, and ensuring on-time delivery for tapeout milestones.