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Power Engineer – AI Accelerator at MatX - ApplyBlast

Power Engineer – AI Accelerator

MatX

3 months ago

Mountain View, California, United States

Hybrid

Full Time

Senior

0 applicants

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About this role

MatX is seeking an experienced engineer to develop and maintain power estimation methodologies for AI accelerator SoCs, build energy models for architectural exploration, and perform RTL, gate‑level, and post‑layout power analysis across major subsystems. The role involves collaborating with architects, RTL designers, and physical design teams to drive power optimization and present findings to cross‑functional groups.

Responsibilities

Develop and maintain power estimation methodologies for AI accelerator SoCs
Perform RTL, gate‑level, and post‑layout power analysis across major SoC subsystems
Drive power optimization across compute, memory, interconnect, and other SoC subsystems

Skills

Qualifications

BS in Electrical EngineeringMS in Electrical Engineering

About MatX

matx.com

Headquarters

Mountain View, California, United States

Company Size

1-10 employees

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MatX designs high-throughput chips and systems purpose-built for large transformer AI models, with their MatX One chip delivering leading FLOPS/mm2, low-latency decode, and the most scale-up interconnect of any announced product. Supporting clusters of hundreds of thousands of chips, MatX targets training, RL, and inference workloads for large dense and MoE models with no upper limit on model size, serving the large model needs of frontier labs. MatX provides a programming model that gives users direct hardware control, with weights typically in SRAM for low latency and KVs in HBM for long-context support.