Cadence
A Senior SoC Verification Engineer at Cadence develops and executes verification plans for complex SoC subsystems and full-chip environments using UVM-based methodologies. The role requires deep expertise in SystemVerilog, protocol knowledge, and debugging functional issues across RTL and integration layers to ensure design intent and testability.
Headquarters
San Jose, California, United States
Company Size
10001+ employees
Founded
1988
Cadence is a company specializing in electronic design automation (EDA) software and engineering services for the semiconductor and electronics industries. Their tools enable design and verification of integrated circuits, systems on chips, and electronics systems, streamlining the development process for engineers and designers. With a commitment to innovation and excellence, Cadence empowers companies to enhance product performance and reduce time to market through advanced simulation, verification, and design tools.
Headquarters
San Francisco, CA
Company Size
201-500 employees
Founded
2018
Industry
Technology
Glassdoor Rating
4.2 / 5
Sarah Johnson
Chief Executive Officer
Michael Chen
Chief Technology Officer
Emily Williams
VP of Engineering
David Rodriguez
VP of Product
Jessica Thompson
Chief Financial Officer
Andrew Park
VP of Sales
View leadership team, funding history,
and employee contacts for Cadence.
Cadence didn’t post a salary, so this is our estimate from similar listings.
41% above the average for this role
Is It Time To Reassess Cadence Design Systems (CDNS) After Its Strong 1-Year Share Price Gain?
1 day ago