Principal ASIC Physical Design Engineer

K2 seeks a Principal ASIC Physical Design Engineer to lead the implementation of complex System-on-Chip (SoC) architectures for next-generation high-power satellites. This senior role requires owning the entire RTL-to-GDSII physical design flow, driving timing closure, and managing external design partners to ensure first-pass silicon success in advanced FinFET processes. The engineer will collaborate across architecture, verification, and packaging teams to deliver state-of-the-art mixed-signal SoCs hosted on rapidly manufactured spacecraft ranging from LEO to deep space missions.