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Principal Design Engineer(Virtual Solution) at Cadence - ApplyBlast

Principal Design Engineer(Virtual Solution)

Cadence

4 months ago

4.0 on Glassdoor

Shanghai, China

Onsite

Full Time

Senior

0 applicants

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About this role

This role involves designing and developing system-level Accelerated Verification IP (AVIP) solutions for emulation and prototyping platforms. The candidate will architect scalable validation environments for complex SoC and subsystems, integrating high-speed protocols and custom automation tools. Collaboration with cross-functional teams is essential for debugging, customer enablement, and evolving next-generation verification methodologies.

Responsibilities

Design and develop system-level AVIP solutions for emulation platforms
Build and integrate Accelerated Verification IP environments for complex SoCs
Develop end-to-end verification flows including testbench and system modeling
Architect scalable solutions for multi-protocol system validation across clock domains
Collaborate with cross-functional teams to debug and resolve system-level issues

Skills

Qualifications

BS in Electrical EngineeringBS in Computer Engineering

About Cadence

cadence.com

Headquarters

San Jose, California, United States

Company Size

10001+ employees

Founded

1988

View Profile

Cadence is a company specializing in electronic design automation (EDA) software and engineering services for the semiconductor and electronics industries. Their tools enable design and verification of integrated circuits, systems on chips, and electronics systems, streamlining the development process for engineers and designers. With a commitment to innovation and excellence, Cadence empowers companies to enhance product performance and reduce time to market through advanced simulation, verification, and design tools.