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Principal Design Verification Engineer at Astera Labs - ApplyBlast

Principal Design Verification Engineer

Astera Labs

24 days ago

4.3 on Glassdoor

San Jose, California, United States

Onsite

Full Time

Senior

0 applicants

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About this role

Astera Labs is seeking a Principal Design Verification Engineer to lead the functional verification of advanced ASICs for server and networking applications. The role involves developing robust verification methodologies, collaborating with cross-functional teams, and ensuring comprehensive coverage closure for cutting-edge SoC designs. This position requires strong problem-solving skills and expertise in SystemVerilog/UVM to drive verification strategy and debug design issues.

Responsibilities

Lead functional verification of advanced ASICs including test planning and coverage analysis
Collaborate with software and system validation teams to execute test plans on emulation platforms
Debug test failures and resolve design issues with RTL designers to ensure comprehensive verification

Skills

About Astera Labs

asteralabs.com

Headquarters

Santa Clara, California, United States

Company Size

201-500 employees

Founded

2017

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Astera Labs is a semiconductor company that builds purpose‑built connectivity silicon and system solutions for rack‑scale AI and modern data centers. They design high‑speed retimers, PHY/connectivity devices, interposers and companion firmware/software that extend signal reach, improve link reliability, and enable PCIe/CXL and other accelerator interconnects across cables and backplanes. Astera’s products add telemetry, error monitoring and management features to simplify integration for OEMs, cloud providers and hyperscalers. The company focuses on enabling scalable, low‑latency multi‑node AI training and inference systems.