Principal Engineer, Design For Test

A Digital IC Design Principal Engineer on Marvell’s Custom Silicon Engineering team focused on architecting and implementing design-for-test (DFT) solutions for complex custom/compute ASIC and SoC designs. The role supports multi-die, high-performance compute and acceleration applications across AI and next-generation carrier architectures. The position involves advancing DFT methodologies and tools while contributing to validation and post-silicon bring-up activities.