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© All Rights Reserved. ApplyBlast.com
SiFive
SiFive is seeking a principal-level hardware engineer to design industry-leading CPU and interconnect IP, specifically focusing on TileLink architectures and RISC-V adoption. The role involves architecting highly-configurable hardware generators using the Chisel library in Scala, enhancing multi-core coherence, and integrating designs into the company's verification framework. This position requires deep expertise in RTL design, bus protocols, and functional programming to deliver high-performance infrastructure logic.
Headquarters
Santa Clara, California, United States
Company Size
501-1000 employees
Founded
2015
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world.
Headquarters
San Francisco, CA
Company Size
201-500 employees
Founded
2018
Industry
Technology
Glassdoor Rating
4.2 / 5
Sarah Johnson
Chief Executive Officer
Michael Chen
Chief Technology Officer
Emily Williams
VP of Engineering
David Rodriguez
VP of Product
Jessica Thompson
Chief Financial Officer
Andrew Park
VP of Sales
View leadership team, funding history,
and employee contacts for SiFive.
48% above the average for this role
SiFive to Power Next-Gen RISC-V AI Data Centers with NVIDIA NVLink Fusion
Jan 15, 2026
