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Principal PCS/PMA RTL Design Engineer at Astera Labs - ApplyBlast

Principal PCS/PMA RTL Design Engineer

Astera Labs

11 hours ago

4.3 on Glassdoor

San Jose, California, United States

Onsite

Full Time

Senior

0 applicants

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About this role

Astera Labs is seeking a Principal PCS/PMA RTL Design Engineer to join its San Jose design team, focusing on the Physical Coding Sublayer (PCS) and Physical Medium Attachment (PMA) logic for high-speed interconnect standards. The role involves contributing to the architecture, implementation, integration, and verification of PCS/PMA digital logic for high-performance connectivity and networking ASICs. This hands-on opportunity allows engineers to build expertise in multi-protocol, multi-lane PHY digital design and contribute to next-generation AI and cloud infrastructure products.

Responsibilities

Develop synthesizable Verilog and SystemVerilog RTL for PCS and PMA digital blocks
Implement PCS functions including line encoding, scrambling, and forward error correction
Support logic synthesis, timing analysis, and design implementation flows for high-speed designs

Skills

About Astera Labs

asteralabs.com

Headquarters

Santa Clara, California, United States

Company Size

201-500 employees

Founded

2017

View Profile

Astera Labs is a semiconductor company that builds purpose‑built connectivity silicon and system solutions for rack‑scale AI and modern data centers. They design high‑speed retimers, PHY/connectivity devices, interposers and companion firmware/software that extend signal reach, improve link reliability, and enable PCIe/CXL and other accelerator interconnects across cables and backplanes. Astera’s products add telemetry, error monitoring and management features to simplify integration for OEMs, cloud providers and hyperscalers. The company focuses on enabling scalable, low‑latency multi‑node AI training and inference systems.